The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Dec. 23, 2009
Ulf Meiertoberens, Stocksund, SE;
Raymond Strickland, Indianapolis, IN (US);
Harvey Buck, Jr., Indianapolis, IN (US);
Michael J. Celentano, Fishers, IN (US);
Peter Sabol, Columbia City, IN (US);
Urs Anliker, Guemligen, CH;
Thomas Von Bueren, Bern, CH;
Jean-noel Fehr, Neuenburg, CH;
Markus Oberli, Kirchberg, CH;
Marcel Frikart, Ostermundigen, CH;
Markus Jungen, Bolligen, CH;
Ulf Meiertoberens, Stocksund, SE;
Raymond Strickland, Indianapolis, IN (US);
Harvey Buck, Jr., Indianapolis, IN (US);
Michael J. Celentano, Fishers, IN (US);
Peter Sabol, Columbia City, IN (US);
Urs Anliker, Guemligen, CH;
Thomas von Bueren, Bern, CH;
Jean-Noel Fehr, Neuenburg, CH;
Markus Oberli, Kirchberg, CH;
Marcel Frikart, Ostermundigen, CH;
Markus Jungen, Bolligen, CH;
Roche Diagnostics Operations, Inc., Indianapolis, IN (US);
Roche Diagnostics International Ltd., Steinhausen, CH;
Abstract
An electronic device may communicate wirelessly with another electronic device. The electronic device may include a first processor configured to control only wireless communications with the another device but not operations associated only with the electronic device, a second processor configured to control the operations associated only with the electronic device but not the wireless communications with the another device, and a memory device connected between the first and second processors. The first and second processors may each be configured to exchange information with the memory device separately and independently of the exchange of information by the other of the first and second processors with the memory device.