The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Jun. 01, 2012
Pradeep Nagarajan, Santa Clara, CA (US);
Yan Chong, San Jose, CA (US);
Sean Shau-tu LU, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, Morgan Hill, CA (US);
Pradeep Nagarajan, Santa Clara, CA (US);
Yan Chong, San Jose, CA (US);
Sean Shau-Tu Lu, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, Morgan Hill, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A circuit includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.