The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2014

Filed:

Mar. 09, 2012
Applicants:

Wei-leun Fang, Hsinchu, TW;

Chia Han Lin, Hsinchu, TW;

Feng Yu Lee, Hsinchu, TW;

Inventors:

Wei-leun Fang, Hsinchu, TW;

Chia Han Lin, Hsinchu, TW;

Feng Yu Lee, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.


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