The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2014
Filed:
Jun. 23, 2010
Gerd K. Bayer, Boeblingen, DE;
David F. Craddock, New Paltz, NY (US);
Thomas A. Gregg, Highland, NY (US);
Michael Jung, Frankfurt am Main, DE;
Andreas Kohler, Boeblingen, DE;
Elke G. Nass, Boeblingen, DE;
Oliver G. Schlag, Weil im Schoenbuch, DE;
Peter K. Szwed, Rhinebeck, NY (US);
Gerd K. Bayer, Boeblingen, DE;
David F. Craddock, New Paltz, NY (US);
Thomas A. Gregg, Highland, NY (US);
Michael Jung, Frankfurt am Main, DE;
Andreas Kohler, Boeblingen, DE;
Elke G. Nass, Boeblingen, DE;
Oliver G. Schlag, Weil im Schoenbuch, DE;
Peter K. Szwed, Rhinebeck, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node.