The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2014
Filed:
Dec. 03, 2010
Patrick A. Buckland, Austin, TX (US);
Jay R. Herring, Poughkeepsie, NY (US);
Gregory M. Nordstrom, Pine Island, MN (US);
William A. Thompson, Rochester, MN (US);
Patrick A. Buckland, Austin, TX (US);
Jay R. Herring, Poughkeepsie, NY (US);
Gregory M. Nordstrom, Pine Island, MN (US);
William A. Thompson, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.