The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2014

Filed:

Aug. 08, 2011
Applicants:

Joseph Lucian Smolenski, Niskayuna, NY (US);

Michael Schutten, Niskayuna, NY (US);

Eladio Clemente Delgado, Niskayuna, NY (US);

Richard Alfred Beaupre, Niskayuna, NY (US);

Inventors:

Joseph Lucian Smolenski, Niskayuna, NY (US);

Michael Schutten, Niskayuna, NY (US);

Eladio Clemente Delgado, Niskayuna, NY (US);

Richard Alfred Beaupre, Niskayuna, NY (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
Abstract

A power-converting apparatus, such as a power module, may include a base plate (), a first direct current (DC) bus and a second DC bus (). A power semiconductor component () may be electrically coupled to one of the buses, and may be disposed on a substrate () physically coupled to the base plate. The power semiconductor component may be made from a high-temperature, wide bandgap material, and the substrate may be exposed to a heat flux based on an operational temperature of the power semiconductor component. At least a first capacitor () may be coupled across the first and second DC buses, and at least second and third capacitors () may be respectively coupled across respective ones of the first and second buses and an alternating current (AC) return path. Capacitors () may each be located inside the power module to establish circuit connections sufficiently proximate to the first power semiconductor component to reduce a formation of parasitic inductances, and further may each be located physically apart from the substrate and thus not exposed to the heat flux.


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