Synchronous semiconductor device having delay locked loop for latency control

Abstract

A synchronous semiconductor device includes an internal command generation unit configured to generate an internal command corresponding to a source command, a delay locked loop configured to delay a source clock by a first delay time required for delay-locking to generate a delay locked clock, a delay time determination unit configured to determine a second delay time for delay-locking the internal command using the source clock, the second delay time being determined by reflecting a third delay time generated on a command path, and a latency control unit configured to shift the internal command by a shifting period, in which the second delay time is reflected, in response to the delay locked clock.