The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2014
Filed:
Jul. 13, 2011
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Google Inc., Mountain View, CA (US);
Abstract
An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.