The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2014

Filed:

Feb. 11, 2011
Applicants:

Hiromitsu Kimura, Kyoto, JP;

Jun Iida, Kyoto, JP;

Koji Nigoriike, Kyoto, JP;

Yoshinobu Ichida, Kyoto, JP;

Inventors:

Hiromitsu Kimura, Kyoto, JP;

Jun Iida, Kyoto, JP;

Koji Nigoriike, Kyoto, JP;

Yoshinobu Ichida, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NANDand NAND) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).


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