The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2014
Filed:
Nov. 21, 2011
Deepak Pancholi, Spandana, IN;
Bhavin Odedara, Kodihalli, IN;
Naidu Prasad, New Tippasandra, IN;
Srikanth Bojja, Ejipura, IN;
Srinivasa Rao Sabbineni, C.V. Raman Nagar, IN;
Jayaprakash Naradasi, Jalahalli Post, IN;
Deepak Pancholi, Spandana, IN;
Bhavin Odedara, Kodihalli, IN;
Naidu Prasad, New Tippasandra, IN;
Srikanth Bojja, Ejipura, IN;
Srinivasa Rao Sabbineni, C.V. Raman Nagar, IN;
Jayaprakash Naradasi, Jalahalli Post, IN;
SanDisk Technologies Inc., Plano, TX (US);
Abstract
A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.