Mechanism for carryless multiplication that employs booth encoding

Abstract

An apparatus having operand registers, an opcode detector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode detector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result.