The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2014

Filed:

May. 26, 2011
Applicants:

Clifford A. King, Gloucester, MA (US);

Conor S. Rafferty, Newton, MA (US);

Inventors:

Clifford A. King, Gloucester, MA (US);

Conor S. Rafferty, Newton, MA (US);

Assignee:

Infrared Newco, Inc., Tucson, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01); H01L 31/06 (2012.01); H01L 29/732 (2006.01); H01L 31/0328 (2006.01); H01L 31/0336 (2006.01); H01L 31/072 (2012.01); H01L 31/109 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.


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