The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2014
Filed:
Mar. 23, 2012
Ji-young Kim, Los Angeles, CA (US);
Kang L. Wang, Santa Monica, CA (US);
Yong-jik Park, Gyeonggi-do, KR;
Jeong-hee Han, Gyeonggi-do, KR;
Augustin Jinwoo Hong, Los Angeles, CA (US);
Ji-Young Kim, Los Angeles, CA (US);
Kang L. Wang, Santa Monica, CA (US);
Yong-Jik Park, Gyeonggi-do, KR;
Jeong-Hee Han, Gyeonggi-do, KR;
Augustin Jinwoo Hong, Los Angeles, CA (US);
Samsung Electronics Co., Ltd., , KR;
The Regents of the University of California, Oakland, CA (US);
Abstract
Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.