The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2014

Filed:

Aug. 30, 2011
Applicants:

Heung-kyu Park, Gumi-si, KR;

In-sun Park, Seoul, KR;

In-gyu Baek, Seoul, KR;

Byeong-chan Lee, Yongin-si, KR;

Sang-bom Kang, Seoul, KR;

Woo-bin Song, Hwaseong-si, KR;

Inventors:

Heung-Kyu Park, Gumi-si, KR;

In-Sun Park, Seoul, KR;

In-Gyu Baek, Seoul, KR;

Byeong-Chan Lee, Yongin-si, KR;

Sang-Bom Kang, Seoul, KR;

Woo-Bin Song, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.


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