The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2014
Filed:
Sep. 14, 2012
Ramamurthy Vishweshwara, Jayanagar, IN;
Mahita Nagabhiru, Andhrapradesh, IN;
Venkatraman Ramakrishnan, Kasturi Nagar, IN;
Ramamurthy Vishweshwara, Jayanagar, IN;
Mahita Nagabhiru, Andhrapradesh, IN;
Venkatraman Ramakrishnan, Kasturi Nagar, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.