The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2014

Filed:

Aug. 23, 2012
Applicants:

Young-deuk Jeon, Daejeon, KR;

Woo Seok Yang, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Jong-kee Kwon, Daejeon, KR;

Jongdae Kim, Daejeon, KR;

Inventors:

Young-deuk Jeon, Daejeon, KR;

Woo Seok Yang, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Jong-Kee Kwon, Daejeon, KR;

Jongdae Kim, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.


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