The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8656336 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 18, 2014

Filed:

Feb. 27, 2012
Applicants:

Piyush Pathak, Sunnyvale, CA (US);

Shobhit Malik, Sunnyvale, CA (US);

Sriram Madhavan, Santa Clara, CA (US);

Inventors:

Piyush Pathak, Sunnyvale, CA (US);

Shobhit Malik, Sunnyvale, CA (US);

Sriram Madhavan, Santa Clara, CA (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature.


Find Patent Forward Citations

Pathak, Piyush. (2014). Pattern based method for identifying design for manufacturing improvement in a semiconductor device (U.S. Patent No. 8656336). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8656336

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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