Apparatus and method for encoding and decoding block low density parity check codes with a variable coding rate

Abstract

A matrix multiplier multiplies the signal output from a first adder by an inverse matrix Tof a partial matrix T of a parent parity check matrix, and outputs the multiplication result to a first switch. The output of the matrix multiplier becomes a second parity vector P. A second switch is switched on at a transmission time of the information word vector 's', a third switch is switched on at a transmission time of the first parity vector P, and the first switch is switched on at a transmission time of the second parity vector P. When a puncturing scheme is applied to the parent parity check matrix, a controller controls the first and second switches to puncture the parity according to the corresponding coding rate.