The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
May. 24, 2011
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Ii, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, II, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.