The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Feb. 28, 2011
Yong-duck Son, Yongin, KR;
Ki-young Lee, Yongin, KR;
Jin-wook Seo, Yongin, KR;
Min-jae Jeong, Yongin, KR;
Byung-soo SO, Yongin, KR;
Seung-kyu Park, Yongin, KR;
Kii-won Lee, Yongin, KR;
Yun-mo Chung, Yongin, KR;
Byoung-keon Park, Yongin, KR;
Dong-hyun Lee, Yongin, KR;
Jong-ryuk Park, Yongin, KR;
Tak-young Lee, Yongin, KR;
Jae-wan Jung, Yongin, KR;
Yong-Duck Son, Yongin, KR;
Ki-Young Lee, Yongin, KR;
Jin-Wook Seo, Yongin, KR;
Min-Jae Jeong, Yongin, KR;
Byung-Soo So, Yongin, KR;
Seung-Kyu Park, Yongin, KR;
Kii-Won Lee, Yongin, KR;
Yun-Mo Chung, Yongin, KR;
Byoung-Keon Park, Yongin, KR;
Dong-Hyun Lee, Yongin, KR;
Jong-Ryuk Park, Yongin, KR;
Tak-Young Lee, Yongin, KR;
Jae-Wan Jung, Yongin, KR;
Samsung Display Co., Ltd., Yongin, KR;
Abstract
A thin film transistor including: an active layer formed on a substrate; a gate insulating layer pattern formed on a predetermined region of the active layer; a gate electrode formed on a predetermined region of the gate insulating layer pattern; an etching preventing layer pattern covering the gate insulating layer pattern and the gate electrode; and a source member and a drain member formed on the active layer and the etching preventing layer pattern.