The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2014
Filed:
Mar. 21, 2012
Scott J. Weber, Piedmont, CA (US);
Christopher D. Ebeling, San Jose, CA (US);
Andrew Caldwell, Santa Clara, CA (US);
Steven Teig, Menlo Park, CA (US);
Timothy J. Callahan, Mantorville, MN (US);
Hung Q. Nguyen, San Jose, CA (US);
Shangzhi Sun, San Jose, CA (US);
Shilpa V. Yeole, Milpitas, CA (US);
Scott J. Weber, Piedmont, CA (US);
Christopher D. Ebeling, San Jose, CA (US);
Andrew Caldwell, Santa Clara, CA (US);
Steven Teig, Menlo Park, CA (US);
Timothy J. Callahan, Mantorville, MN (US);
Hung Q. Nguyen, San Jose, CA (US);
Shangzhi Sun, San Jose, CA (US);
Shilpa V. Yeole, Milpitas, CA (US);
Tabula, Inc., Santa Clara, CA (US);
Abstract
A novel method for designing an integrated circuit ('IC') by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.