The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2014

Filed:

Jan. 30, 2009
Applicants:

Shuxian Wu, San Jose, CA (US);

Tao Yu, San Jose, CA (US);

Inventors:

Shuxian Wu, San Jose, CA (US);

Tao Yu, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Modeling and simulating behavior of a transistor are described. At least one sub-circuit model for modeling at least one second order effect associated with the transistor is obtained. At least one instance parameter for the at least one second order effect is obtained. Operation of a transistor behavior simulator is augmented with the at least one sub-circuit model populated with the at least one instance parameter such that the simulating of the behavior of the transistor produces data that takes into account the at least one second order effect. The at least one second order effect may be an LOD/eSiGe effect, a poly pitch effect, or a DSL boundary effect. Also described is a method for generation of a sub-circuit model.


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