The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2014

Filed:

Nov. 24, 2008
Applicants:

Jincheol Hong, Kyungbuk, KR;

Sungjo Koo, Daegu, KR;

Suhyuk Jang, Daegu, KR;

Inventors:

Jincheol Hong, Kyungbuk, KR;

Sungjo Koo, Daegu, KR;

Suhyuk Jang, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display and driving method thereof are disclosed. The liquid crystal display according to an embodiment of the invention includes a liquid crystal panel having liquid crystal cells in a matrix array at crossings of data lines and gate lines; a timing controller for receiving a digital video data and synchronous signals, and generating a source output enable signal, a first gate start pulse, a second gate start pulse having a pulse width different from that of the first gate start pulse, a gate shift clock, a first gate output enable signal and a second gate output enable signal; a data driving circuit for providing a data voltage to the data lines in response to a first logic value of the source output enable signal, and any one black gray voltage of a charge share voltage and a precharge voltage to the data lines in response to a second logic value of the source output enable signal; and a gate driving circuit for providing a first gate pulse in synchronization with the data voltage and a second gate pulse in synchronization with the black gray voltage to the gate lines, in response to the first gate start pulse, the second gate start pulse, the gate shift clock, the first gate output enable signal and the second gate output enable signal.


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