The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
Jun. 21, 2012
Rajan Aggarwal, New Delhi, IN;
Ashutosh Anand, Bangalore, IN;
Ankit Bhargava, Delhi, IN;
Mishika Singla, Patiala, IN;
Prashant K. Sonone, Akola, IN;
Rajan Aggarwal, New Delhi, IN;
Ashutosh Anand, Bangalore, IN;
Ankit Bhargava, Delhi, IN;
Mishika Singla, Patiala, IN;
Prashant K. Sonone, Akola, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit.