The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
May. 07, 2012
Brett W. Coon, San Jose, CA (US);
Ming Y. Siu, Santa Clara, CA (US);
Weizhong Xu, Fremont, CA (US);
Stuart F. Oberman, Sunnyvale, CA (US);
John R. Nickolls, Los Altos, CA (US);
Peter C. Mills, San Jose, CA (US);
Brett W. Coon, San Jose, CA (US);
Ming Y. Siu, Santa Clara, CA (US);
Weizhong Xu, Fremont, CA (US);
Stuart F. Oberman, Sunnyvale, CA (US);
John R. Nickolls, Los Altos, CA (US);
Peter C. Mills, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.