The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

May. 04, 2012
Applicants:

Albert M. Chu, Nashua, NH (US);

Joseph A. Iadanza, Hinesburg, VT (US);

Mujahid Muhammad, Essex Junction, VT (US);

Daryl M. Seitzer, Essex Junction, VT (US);

Rohit Shetty, Essex Junction, VT (US);

Jane S. Tu, Prospect Heights, IL (US);

Inventors:

Albert M. Chu, Nashua, NH (US);

Joseph A. Iadanza, Hinesburg, VT (US);

Mujahid Muhammad, Essex Junction, VT (US);

Daryl M. Seitzer, Essex Junction, VT (US);

Rohit Shetty, Essex Junction, VT (US);

Jane S. Tu, Prospect Heights, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 3/20 (2006.01); H02H 9/04 (2006.01); H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.


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