The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Jun. 30, 2005
Applicants:
Douglas R. Sullivan, Hopkinton, MA (US);
Howard G. Drake, Westborough, MA (US);
Matthew Yellen, Worcester, MA (US);
Inventors:
Douglas R. Sullivan, Hopkinton, MA (US);
Howard G. Drake, Westborough, MA (US);
Matthew Yellen, Worcester, MA (US);
Assignee:
EMC Corporation, Hopkinton, MA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract
A diplex FPGA is utilized to fan out a single high speed host universal asynchronous receiver transmitter ('UART') channel into a number of diplex UART channels. The diplex FPGA includes a microprocessor, memory, a host UART and a number of diplex UARTs. In operation, the microprocessor polls each of the UARTs in a 'round robin' manner and accepts packets from the host UART for transmission downstream and from the diplex UARTs for transmission upstream.