The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2014

Filed:

Aug. 24, 2007
Applicants:

Akira Ito, Irvine, CA (US);

Henry Kuoshun Chen, Irvine, CA (US);

Inventors:

Akira Ito, Irvine, CA (US);

Henry KuoShun Chen, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01); H01L 21/332 (2006.01); H01L 21/4763 (2006.01); H01L 21/3205 (2006.01); H01L 21/04 (2006.01); H01L 29/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.


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