The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2014

Filed:

Oct. 12, 2009
Applicants:

Gilberto Curatola, Korbek-Lo, BE;

Marcus J. H. Van Dal, Heverlee, NL;

Inventors:

Gilberto Curatola, Korbek-Lo, BE;

Marcus J. H. Van Dal, Heverlee, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate () using a patterned hard mask () covering the higher steps of said profile; forming a gate stack () against the side wall of the higher step; forming spacers () on either side of the gate stack (); and implanting a first type impurity () in the higher step and an opposite type impurity in the neighboring lower step (), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (). In a preferred embodiment, the method further comprises forming a sacrificial spacer () against a side wall of a higher step and the side wall of the hard mask (); further etching the lower step () next to said spacer () and subsequently growing a further semiconductor portion () on said lower step and removing the spacer () prior to forming the gate stack. Further disclosed is an IC comprising tunnel transistors manufactured in accordance with this method.


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