The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2014

Filed:

Feb. 03, 2012
Applicants:

Alain Benayoun, Cagnes sur Mer, FR;

Jean-francois Le Pennec, Nice, FR;

Patrick Michel, La Gaude, FR;

Claude Pin, Nice, FR;

Inventors:

Alain Benayoun, Cagnes sur Mer, FR;

Jean-Francois Le Pennec, Nice, FR;

Patrick Michel, La Gaude, FR;

Claude Pin, Nice, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 15/76 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.


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