The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Jun. 28, 2012
Jayarama Ubaradka, Bangalore, IN;
Dharmaray M. Nedalgi, Bangalore, IN;
Jayarama Ubaradka, Bangalore, IN;
Dharmaray M. Nedalgi, Bangalore, IN;
NXP, B.V., Eindhoven, NL;
Abstract
State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.