The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Feb. 22, 2011
Asao Nishimura, Kokubunji, JP;
Syouji Syukuri, Koganei, JP;
Gorou Kitsukawa, Kisarazu, JP;
Toshio Miyamoto, Kokubunji, JP;
Asao Nishimura, Kokubunji, JP;
Syouji Syukuri, Koganei, JP;
Gorou Kitsukawa, Kisarazu, JP;
Toshio Miyamoto, Kokubunji, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
In a semiconductor integrated circuit device, testing pads () using a conductive layer, such as relocation wiring layers () are provided just above or in the neighborhood of terminals like bonding pads () used only for probe inspection at which bump electrodes () are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.