The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Jul. 14, 2010
Jing Chen, Shanghai, CN;
Jiexin Luo, Shanghai, CN;
Qingqing Wu, Shanghai, CN;
Jianhua Zhou, Shanghai, CN;
Xiaolu Huang, Shanghai, CN;
Xi Wang, Shanghai, CN;
Jing Chen, Shanghai, CN;
Jiexin Luo, Shanghai, CN;
Qingqing Wu, Shanghai, CN;
Jianhua Zhou, Shanghai, CN;
Xiaolu Huang, Shanghai, CN;
Xi Wang, Shanghai, CN;
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Changning District, Sanghai, CN;
Abstract
The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost.