The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Jun. 15, 2011
Brett M. Diamond, Pittsburgh, PA (US);
Franz Laermer, Weil der Stadt, DE;
Andrew J. Doller, Sharpsburg, PA (US);
Michael J. Daley, Canonsburg, PA (US);
Phillip Sean Stetson, Wexford, PA (US);
John M. Muza, Venetia, PA (US);
Brett M. Diamond, Pittsburgh, PA (US);
Franz Laermer, Weil der Stadt, DE;
Andrew J. Doller, Sharpsburg, PA (US);
Michael J. Daley, Canonsburg, PA (US);
Phillip Sean Stetson, Wexford, PA (US);
John M. Muza, Venetia, PA (US);
Robert Bosch GmbH, Stuttgart, DE;
Abstract
A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.