The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Feb. 03, 2012
Thomas Buechner, Weil im Schoenbuch, DE;
Markus Buehler, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Schoenaich, DE;
Lei Wang, Hannover, DE;
Thomas Buechner, Weil im Schoenbuch, DE;
Markus Buehler, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Schoenaich, DE;
Lei Wang, Hannover, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.