The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Oct. 29, 2010
Kiran Vedantam, Santa Clara, CA (US);
James G. Ballard, Palo Alto, CA (US);
Miao Rao, San Jose, CA (US);
Guneet Singh, San Jose, CA (US);
Wanyun Singh, Fremont, CA (US);
Kiran Vedantam, Santa Clara, CA (US);
James G. Ballard, Palo Alto, CA (US);
Miao Rao, San Jose, CA (US);
Guneet Singh, San Jose, CA (US);
Wanyun Singh, Fremont, CA (US);
Oracle International Corporation, Redwood City, CA (US);
Abstract
Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.