Decoding device and decoding method

Abstract

A multistage difference cyclic permutation unit () for performing multistage cyclic permutation, an address administration unit () for administering addresses of the cumulative LLR memory (), a received value arrangement unit () for generating records during writing of received values to the cumulative LLR memory (), and a control unit () for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit () controls reading/writing addresses of the cumulative LLR memory () based on a reading start address from the cumulative LLR memory () corresponding to the column block. After the start of reading of a column block, the control unit () generates a reading start address in the next decoding of the column block and stores it into the address administration unit (). In this manner, a device configuration capable of reducing a device size of a decoding device for pseudo-cyclic LDPC codes composed of cyclic permutation matrix blocks with a fixed degree of parallelism and an arbitrary cyclic permutation size is provided.