The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2014

Filed:

Aug. 07, 2007
Applicant:

Gyle D Yearsley, Boise, ID (US);

Inventor:

Gyle D Yearsley, Boise, ID (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a tamper detection system, a control system controls power consumption by sensors and power consumption of a state machine that controls operations of the sensors. A first state machine controls which sensor is activated. A second state machine controls the operations performed by the activated sensor and the operations are timed according to a clock signal. Prior to activating a sensor, the second state machine is in a wait state. The clock signal is gated so that the logic state of the clock signal does not change when the second state machine is in a wait state. Power consumption by the state machine is reduced by gating the clock signal so that the clock signal is held to a fixed value. Immediately after the activated sensor performs all operations, the second state machine samples the pass or fail result from the sensor. Power consumption by the activated sensor is reduced by sampling the pass or fail result of the sensor immediately after the sensor performs the last operation and immediately turning off the sensor after sampling the pass or fail result. The second state machine enters another wait state after sampling of the pass or fail result.


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