The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Mar. 14, 2006
Tao LI, San Diego, CA (US);
Christian Holenstein, San Diego, CA (US);
Inyup Kang, San Diego, CA (US);
Brett C. Walker, San Diego, CA (US);
Paul E. Peterzell, San Diego, CA (US);
Raghu Challa, San Diego, CA (US);
Matthew L. Severson, Oceanside, CA (US);
Arun Raghupathy, San Diego, CA (US);
Gilbert Christopher Sih, San Diego, CA (US);
Tao Li, San Diego, CA (US);
Christian Holenstein, San Diego, CA (US);
Inyup Kang, San Diego, CA (US);
Brett C. Walker, San Diego, CA (US);
Paul E. Peterzell, San Diego, CA (US);
Raghu Challa, San Diego, CA (US);
Matthew L. Severson, Oceanside, CA (US);
Arun Raghupathy, San Diego, CA (US);
Gilbert Christopher Sih, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.