The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2014

Filed:

Apr. 01, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Narayan Kulshrestha, Fremont, CA (US);

Adam Paul Dreyer, Portland, OR (US);

Chad D. Walker, San Jose, CA (US);

Rui M. Bastos, Porto Alegra, BR;

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/00 (2006.01); G06F 13/00 (2006.01); G09G 5/36 (2006.01); G06F 12/00 (2006.01); G06F 15/00 (2006.01); G06F 9/00 (2006.01); G06K 9/60 (2006.01); H04N 1/46 (2006.01); G03F 3/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.


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