The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Feb. 24, 2012
Suku Kim, South Jordan, UT (US);
James Murphy, South Jordan, UT (US);
Matthew Reynolds, Sandy, UT (US);
Romel Manatad, Mandaue, PH;
Jan Mancelita, Mandaue, PH;
Michael Gruenhagen, Salt Lake City, UT (US);
Suku Kim, South Jordan, UT (US);
James Murphy, South Jordan, UT (US);
Matthew Reynolds, Sandy, UT (US);
Romel Manatad, Mandaue, PH;
Jan Mancelita, Mandaue, PH;
Michael Gruenhagen, Salt Lake City, UT (US);
Fairchild Semiconductor Corporation, San Jose, CA (US);
Abstract
Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.