The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Jan. 11, 2011
Jong-in Kim, Suwon-si, KR;
Young-wook Lee, Suwon-si, KR;
Jean-ho Song, Yongin-si, KR;
Jae-hyoung Yoon, Hwaseong-si, KR;
Sung-ryul Kim, Cheonan-si, KR;
Byeong-beom Kim, Suwon-si, KR;
Je-hyeong Park, Hwaseong-si, KR;
Woo-geun Lee, Yongin-si, KR;
Jong-In Kim, Suwon-si, KR;
Young-Wook Lee, Suwon-si, KR;
Jean-Ho Song, Yongin-si, KR;
Jae-Hyoung Yoon, Hwaseong-si, KR;
Sung-Ryul Kim, Cheonan-si, KR;
Byeong-Beom Kim, Suwon-si, KR;
Je-Hyeong Park, Hwaseong-si, KR;
Woo-Geun Lee, Yongin-si, KR;
Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;
Abstract
A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.