The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2013
Filed:
Oct. 22, 2004
Applicant:
Jesse H. Jenkins, Iv, Danville, CA (US);
Inventor:
Jesse H. Jenkins, IV, Danville, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/16 (2006.01); G06F 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Programmable logic devices (PLDs), programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), (collectively referred to as 'PLDs') can include circuitry for performing automatic erasing or 'zeroization' of security information including data and programming. Such circuitry detects the occurrence of a possible security event, selects and/or forms one or more appropriate erase commands, and causes the command(s) to be executed against PLD memory. The circuitry prevents security information from being compromised under certain situations.