Generating and selecting bit-stack candidates from a graph using dynamic programming

Abstract

Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement.