Method of selecting a set of illumination conditions of a lithographic apparatus for optimizing an integrated circuit physical layout

Abstract

The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number. Polygon patterns are identified as predefined complex circuit elements and wherein the cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit design intent. The cost number functions can further have interdependencies in multiple critical dimensions of the polygon patterns so as to take the two dimensional nature into account.