The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2013
Filed:
Apr. 27, 2012
Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
Kyung-tae DO, Mansan-si, KR;
Yong-seok Lee, Suwon-si, KR;
Hyo-sig Won, Suwon-si, KR;
Jung-yun Choi, Hwaseong-si, KR;
Jong-ho Kim, Seoul, KR;
Kyung-Tae Do, Mansan-si, KR;
Yong-Seok Lee, Suwon-si, KR;
Hyo-Sig Won, Suwon-si, KR;
Jung-Yun Choi, Hwaseong-si, KR;
Jong-Ho Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.