The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

May. 18, 2010
Applicants:

Bharat K. Daga, Fremont, CA (US);

Robert E. Cypher, Saratoga, CA (US);

Inventors:

Bharat K. Daga, Fremont, CA (US);

Robert E. Cypher, Saratoga, CA (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 29/00 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include () a row-checkbit column containing row-parity bits for each of the R rows, () an inner-checkbit column containing X=R−S inner checkbits and S spare bits, and () C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.


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