The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

Feb. 08, 2010
Applicants:

John Henry Bui, Sunnyvale, CA (US);

Triet M. Nguyen, San Jose, CA (US);

Inventors:

John Henry Bui, Sunnyvale, CA (US);

Triet M. Nguyen, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits with memory circuitry are provided. The memory circuitry may include rows of data line segments. Each data line segment may have associated memory cells, a programmable-strength precharge circuit, a latch circuit, a programmable-strength pull-up circuit, and a data line segment buffer. The precharge circuit may include multiple paths that can be switched into use depending on the configuration of programmable bits. The programmable-strength pull-up circuit may include multiple pull-up paths. The number of pull-up paths in use can be configured. The latch circuit may include a latch inverter that enables the programmable latch circuit during precharge operations. During a precharge period, the latch circuit can be disabled to block contending pull-down current and the data line segment buffer can be disabled to avoid crossbar currents.


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