The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

Aug. 26, 2011
Applicants:

Shankar Sinha, Redwood City, CA (US);

Brian Wong, Sunnyvale, CA (US);

Shih-lin S. Lee, San Jose, CA (US);

Abhishek Sharma, San Jose, CA (US);

Inventors:

Shankar Sinha, Redwood City, CA (US);

Brian Wong, Sunnyvale, CA (US);

Shih-Lin S. Lee, San Jose, CA (US);

Abhishek Sharma, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.


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