The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

Dec. 21, 2011
Applicants:

Jason J. Mangattur, Thornhill, CA;

Richard Fung, Thornhill, CA;

Alan Siu Kei Poon, North York, CA;

Inventors:

Jason J. Mangattur, Thornhill, CA;

Richard Fung, Thornhill, CA;

Alan Siu Kei Poon, North York, CA;

Assignee:

ATI Technologies ULC, Markham, Ontario, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level.


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